View CXP81952M_175330.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXP81952M/81960M
CMOS 8-bit Single Chip Microcomputer
Description The CXP81952M/81960M is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, 32kHz timer/event counter, remote control reception circuit, and FRC capture unit, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also the CXP81952M/81960M provides sleep/stop functions which enable to lower power consumption and ultra-low speed instruction mode in 32kHz operation. 100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit operation/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 200ns at 20MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (2.7 to 5.5V) 122s at 32kHz operation * Incorporated ROM capacity 52K bytes (CXP81952M), 60K bytes (CXP81960M) * Incorporated RAM capacity 2048 bytes * Peripheral functions -- A/D converter 8 bits, 12 channels, successive approximation system (Conversion time of 16s at 20MHz) -- Serial Interface Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer), 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter -- High precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels -- PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 78kHz at 20MHz) DA gate pulse output: 13 bits, 4 channels -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits, 1 channel -- Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO * Interruption 20 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP/LQFP * Piggyback/evaluator CXP81900M
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95511A69-PS
Block Diagram
AVREF
PI4/INT1/NMI
AVDD
AVss
SPC700 CPU CORE
PORT B
CLOCK GENERATOR/ SYSTEM CONTROL 8
PORT A
AN0 to AN3 PF0/AN4 to PF7/AN11 2 8 NMI
12
A/D CONVERTER
PE0/INT0
PE1/INT2
TEX TX EXTAL
XTAL RST MP VDD Vss
PA0 to PA7
CS0 SI0 SO0 SCK0 RAM
PORT C
SERIAL INTERFACE UNIT (CH0)
PB0 to PB7
8
PC0 to PC7
PI7/SI1 PI6/SO1 PI5/SCK1 FIFO 2 ROM 52K/60K BYTES RAM 2048 BYTES
INTERRUPT CONTROLLER
SERIAL INTERFACE UNIT (CH1)
PE1/EC
8 BIT TIMER/COUNTER 0
PI3/TO
8 BIT TIMER 1
PORT D
8
PD0 to PD7
2
PORT E
PE0 to PE1 6 4
PORT F
PE2 to PE7 PF0 to PF3
PI2/PWM
14 BIT PWM GENERATOR
32kHz TIMER/COUNTER
PORT G
2 2 4 PROGRAMMABLE PATTERN GENERATOR 19 RAM REALTIME PULSE GENERATOR CH0 5 CH1
12 BIT PWM GENERATOR CH1
PORT H
PORT I
ADJ
PA0/PPO0 to PC2/PPO18
PC3/RTO3 to PC7/RTO7
PORT J
-2-
2 FIFO FRC CAPTURE UNIT FIFO
PG6/EXI0 PG7/EXI1
PI1/RMC
REMOCON INPUT
PRESCALER/ TIME BASE TIMER
4
PF4 to PF7
8
PG0 to PG7
12 BIT PWM GENERATOR CH0
8
PH0 to PH7
PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1
7
PI1 to PI7
8
PJ0 to PJ7
CXP81952M/81960M
CXP81952M/81960M
Pin Assignment 1 (Top View) 100-pin QFP package
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI3/TO/ADJ
PI4/INT1/NMI
VSS
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8
TX
TEX
VDD
PI1/RMC
PI2/PWM
Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND.
-3-
PF7/AN11
PF6/AN10
PF5/AN9
EXTAL
SCK0
XTAL
RST
SO0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
MP
SI0
PI5/SCK1
CXP81952M/81960M
Pin Assignment 2 (Top View) 100-pin LQFP package
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI3/TO/ADJ
PI4/INT1/NMI
PI5/SCK1
PI1/RMC
PI2/PWM
PI6/SO1
VSS
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF
TX
TEX
VDD
PF5/AN9
PF4/AN8
PI7/SI1
Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND.
-4-
PF7/AN11
PF6/AN10
EXTAL
SCK0
XTAL
AVSS
SO0
RST
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
SI0
MP
PE0/INT0
CXP81952M/81960M
Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description
Output/ Real-time output
PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
Output/ Real-time output
Programmable pattern generator (PPG) output. Functions as high precision real-time pulse output port. (19 pins)
I/O/ Real-time output I/O/ Real-time output
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins)
PD0 to PD7
I/O
(Port D) 8-bit I/O port. I/O can be set in a unit of 4bits. Can drive 12mA sink current. (8 pins) Input pin to request external interruption. Active at the falling edge. (Port E) 8-bit port. Lower 2 bits are for input; upper 6 bits are for output. (8 pins) External event input pin for timer/counter. PWM output pins. (2 pins) Input pin to request external interruption. Active at the falling edge.
PE0/INT0
Input/Input
PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0
Input/Input/Input Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input Input/Input
DA gate pulse output pins. (4 pins)
Analog input pins to A/D converter. (12 pins) (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. Lower 4 bits also serve as standby release input pin. (8 pins)
Output/Input I/O Ouput Input Input
Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin.
-5-
CXP81952M/81960M
Symbol PG0 to PG4 PG5 PG6/EXI0 PG7/EXI1 Input
I/O (Port G) 8-bit input port. (8 pins)
Description
External input pin to FRC capture unit.
PH0 to PH7
Output
(Port H) 8-bit output port; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control reception circuit input pin. 14-bit PWM output pin. (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Timer/counter, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non-maskable interruption. Active at the falling edge. Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin. (Port J) 8-bit I/O port. I/O and standby release input can be set in a unit of single bits. Connects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connects a crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) System reset pin; active at Low level. Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter.
PI1/RMC PI2/PWM PI3/TO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD Vss
I/O/Input I/O/Output I/O/Output/Output I/O/Input/Input I/O/I/O I/O/Output I/O/Input I/O Input Output Input Output Input Input
Input
Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND.
-6-
CXP81952M/81960M
Input/Output Circuit Formats for Pins Pin Port A Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15
Data bus RD (Port A or Port B) PPO data
Circuit format
When reset
Port A or Port B
Hi-Z
Output becomes active from high impedance by data writing to port register.
16 pins Port C
PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
PPO, RTO data Port C data IP (Every bit) Data bus RD (Port C) Input protection circuit
Hi-Z
Port C direction
8 pins Port D
PD0 to PD7
Port D data IP (Every 4 bits) PD0 to 3 PD4 to 7 RD (Port D)
Large current 12mA
Hi-Z
Port D direction
Data bus
8 pins
-7-
CXP81952M/81960M
Pin Port E PE0/INT0
Circuit format
When reset
Data bus RD (Port E) Interruption circuit
IP Input protection circuit
Hi-Z
1 pin Port E
PE1/EC/INT2
Data bus RD (Port E) Interruption circuit/ event counter
IP
Hi-Z
Input protection circuit
1 pin
Port E
DA gate output or PWM output
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
Hi-Z control Port E data
MPX
Hi-Z
Port/DA output selection Data bus
4 pins Port E
RD (Port E)
DA gate output Hi-Z control MPX
PE6/DAB0 PE7/DAB1
Port E data
High level
Port/DA output selection Data bus
2 pins
RD (Port E)
-8-
CXP81952M/81960M
Pin
Circuit format
Input multiplexer IP A/D converter
When reset
AN0 to AN3 4 pins Port F
Hi-Z
Input multiplexer
PF0/AN4 to PF3/AN7
IP
A/D converter
Hi-Z
Data bus
4 pins Port F
RD (Port F)
PF4/AN8 to PF7/AN11
Port F data
Data bus RD (Port F) Port/AD selection
Hi-Z
IP A/D converter
4 pins Port G
Schmitt input
Input multiplexer
PG0 to PG5
IP RD (Port G) Data bus
Hi-Z
6 pins Port G
Schmitt input
PG6/EXI0 PG7/EXI1
IP
FRC capture unit Data bus
Hi-Z
2 pins Port H
RD (Port G) Medium drive voltage 12V
PH0 to PH7
Port H data
Hi-Z
Large current 12mA
Data bus
8 pins
RD (Port H)
-9-
CXP81952M/81960M
Pin Port I
Port I function selection PI2 ... From 14-bit PWM PI3 ... From timer/counter, 32kHz timer
Circuit format
When reset
PI2/PWM PI3/TO/ADJ
MPX Port I data Port I direction
Hi-Z
IP
Data bus
2 pins Port I
RD (Port I)
Port I data
PI1/RMC PI4/INT1/NMI PI7/SI1
Data bus
Port I direction
Hi-Z
IP RD (Port I) PI1 ... To remote control circuit PI4 ... To interruption circuit PI7 ... To serial CH1 Schmitt input
3 pins Port I
Port I function selection From serial CH1 Port I data Port I direction MPX Note) PI5 is Schmitt input PI6 is inverter input RD (Port I) To serial CH1
PI5/SCK1 PI6/SO1
MPX
Hi-Z
IP
Data bus
2 pins
- 10 -
CXP81952M/81960M
Pin Port J
Port J data
Circuit format
When reset
Port J direction
PJ0 to PJ7
Data bus RD (Port J) Standby release Data bus RD (Port J direction) Edge detection
IP
Hi-Z
8 pins
CS0 SI0
IP
Schmitt input To SIO
Hi-Z
2 pins
SO0
SO0 from SIO
Hi-Z
1 pin
SO0 output enable
Internal serial clock from SIO
SCK0
SCK0 output enable External serial clock to SIO IP
Hi-Z
1 pin
Schmitt input
EXTAL XTAL
EXTAL
IP
* Diagram shows the circuit composition during oscillation. * Feedback resistor is removed during stop mode.
Oscillation
2 pins
XTAL
- 11 -
CXP81952M/81960M
Pin
Circuit format
32kHz timer counter TEX IP * Diagram shows the circuit composition during oscillation. * Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level.
When reset
TEX TX
Oscillation
2 pins
TX
Mask option
Pull-up resistor Schmitt input
RST
OP
Low level
IP
1 pin
MP
IP CPU mode
Hi-Z
1 pin
- 12 -
CXP81952M/81960M
Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS Input voltage Output voltage Medium drive output voltage High level output current High level total output current Low level output current VIN VOUT VOUTP IOH IOH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD Rating -0.3 to +7.0 AVss to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 600 380 mW Unit V V V V V V mA mA mA mA mA C C QFP LQFP PH pin
(Vss = 0V reference) Remarks
Total of output pins Pins excluding large current outputs (value per pin) Large current output pin (value per pin3) Total of output pins
1 AVDD and VDD should be set to the same voltage. 2 VIN and VOUT should not exceed VDD + 0.3V. 3 The large current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
- 13 -
CXP81952M/81960M
Recommended Operating Conditions Item Symbol Min. 4.5 2.7 Supply voltage VDD 2.7 2.5 2.0 Analog supply voltage AVDD VIH High level input voltage VIHS 2.7 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 5.5 5.5 VDD VDD 5.5 Unit V V V V V V V V V V V V V V V V C
(Vss = 0V reference) Remarks fc = 20MHz or less Guaranteed operation range for high-speed mode (1/2 frequency fc = 12MHz or less dividing clock) Guaranteed operation range for low-speed mode (1/16 frequency dividing clock) Guaranteed operation range by TEX clock Guaranteed data hold range for stop mode 1 2 CMOS Schmitt input3 and PE0/INT0 CMOS Schmitt input6 EXTAL4, 7 and TEX5, 7 EXTAL4, 8 and TEX5, 8 2, 7 2, 8 CMOS Schmitt input3 and PE0/INT0 EXTAL4, 7 and TEX5, 7 EXTAL4, 8 and TEX5, 8
VIHEX
VDD - 0.4 VDD + 0.3 VDD - 0.2 VDD + 0.2 0 0 0.3VDD 0.2VDD 0.2VDD 0.4 0.2 +75
VIL Low level input voltage VILS VILEX Operating temperature Topr 1 2 3 4 5 6 7 8
0 -0.3 -0.3 -20
AVDD and VDD should be set to the same voltage. Normal input ports (PC, PD, PF0 to PF3, PG, PI and PJ), MP SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1 Specifies only when the external clock is input. Specifies only when the external event count clock is input. CS0, SI0 and PG In case of 4.5 to 5.5V supply voltage (VDD). In case of 2.7 to 3.3V supply voltage (VDD).
- 14 -
CXP81952M/81960M
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST1 EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A
VOL
I/O leakage current
IIZ
VDD = 5.5V, VI = 0, 5.5V
10
A
Open drain output leakage current (in N-CH Tr OFF state)
ILOH
PH
VDD = 5.5V VOH = 12V High speed mode (1/2 frequency dividing clock) operation VDD = 5.5V, 20MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Sleep mode 39
50
A
IDD1
60
mA
IDDS1 Supply current2 VDD
39
100
A
IDD2
VDD = 5.5V, 20MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode
2.1
10
mA
IDDS2
7
30
A
IDDS3
VDD = 5.5V, termination of 20MHz and 32kHz oscillation
Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss
10
A
Input capacity
CIN
10
20
pF
1 For RST pin, specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. 2 When all output pins are open.
- 15 -
CXP81952M/81960M
DC Characteristics (VDD = 2.7 to 3.3V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST1 PH EXTAL Conditions VDD = 2.7V, IOH = -0.12mA VDD = 2.7V, IOH = -0.45mA VDD = 2.7V, IOL = 1.0mA VDD = 2.7V, IOL = 1.4mA VDD = 2.7V, IOL = 4.5mA VDD = 3.3V, VIH = 3.3V VDD = 3.3V, VIL = 0.3V VDD = 3.3V, VIH = 3.3V VDD = 3.3V, VIL = 0.3V
(Ta = -20 to +75C, Vss = 0V reference) Min. 2.5 2.1 0.25 0.4 0.9 0.3 -0.3 0.1 -0.1 -0.9 20 -20 10 -10 -200 Typ. Max. Unit V V V V V A A A A A
VOL
I/O leakage current
IIZ
VDD = 3.3V, VI = 0, 3.3V
10
A
Open drain output leakage current
ILOH
VDD = 3.3V, VOH = 12V 12MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.0V 0.3V3 Sleep mode 13
50
A
IDD1
25
mA
Supply current2
IDDS1
VDD
VDD = 3.0V 0.3V Stop mode (EXTAL and TEX pins oscillation stop) VDD = 3.0V 0.3V
0.7
2.0
mA
IDDS3
10
A
Input capacity
CIN
Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss
10
20
pF
1 For RST pin, specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. 2 When all output pins are open. 3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high-speed mode (1/2 dividing clock).
- 16 -
CXP81952M/81960M
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times 1 Symbol fC Pins XTAL EXTAL XTAL EXTAL XTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -20 to +75C, VDD = 2.7 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, VDD = 4.5 to 5.5V VDD = 4.5 to 5.5V Min. 1 1 23 37.5 200 ns ns 20 32.768 10 20 ns kHz s ms Max. 20 12 ns Unit MHz
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
Fig. 2 (External clock drive) Fig. 1, Fig. 2 (External clock drive) Fig. 3 Fig. 3 Fig. 2 VDD = 2.5 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3
tsys x 41
tTL, tTH tTR, tTF
tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2
bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL C1
TEX
TX C2
74HC04
Fig. 3. Event count clock timing
0.8VDD 0.2VDD
TEX EC
tEH tTH
tEF tTF
tEL tTL
tER tTR
- 17 -
CXP81952M/81960M
(2) Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0 and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
- 18 -
CXP81952M/81960M
Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns
tDCSK
tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 150 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0 and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF.
- 19 -
CXP81952M/81960M
Fig. 4. Serial transfer timing (CH0)
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
- 20 -
CXP81952M/81960M
Serial transfer (CH1) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 8000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
4000/fc - 100 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 8000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
4000/fc - 150 100 200
tsys + 200
100
tsys + 250
125
ns ns
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
- 21 -
CXP81952M/81960M
Fig. 5. Serial transfer CH1 timing
tKCY tKL tKH
SCK1 0.8VDD 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
- 22 -
CXP81952M/81960M
(4) A/D converter characteristics (Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN11 Operating mode AVREF IREFS Sleep mode Stop mode 32kHz operating mode VDD = AVDD = 4.5 to 5.5V AVDD - 0.5 0 0.6 1.0 10 AVDD Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage
AVREF current
(Ta = -20 to +75C, VDD = AVDD = 2.7 to 3.3V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25C VDD = AVDD = AVREF = 3.0V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN11 Operating mode AVREF Sleep mode Stop mode 32kHz operating mode VDD = AVDD = 2.7 to 3.3V AVDD - 0.3 0 0.3 0.7 10 AVDD Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage
AVREF current
IREFS
Fig. 6. Definitions of A/D converter terms
FFH FEH
Digital conversion value
1 The value of fADC is as follows by selecting ADC
Linearity error 01H 00H VZT Analog input VFT
operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc
- 23 -
CXP81952M/81960M
(4) Interruption, reset input Item
(Ta = -20 to +75C, VDD = 2.7 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 NMI PJ0 to PJ7 RST Conditions Min. Max. Unit
External interruption High and Low level widths
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
Fig. 7. Interruption input timing
INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge)
tIH
tIL
0.8VDD 0.2VDD
Fig. 8. Reset input timing
tRSL
RST 0.2VDD
(5) Others Item EXI input High and Low level widths Note) Symbol Pins EXI0 EXI1
(Ta = -20 to +75C, VDD = 2.7 to 5.5V, Vss = 0V reference) Conditions Min. Max. Unit ns
tEIH tEIL
tsys = 2000/fc
tFRC x 8 + 200 + tsys
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC = 1000/fc [ns]
Fig. 9. Other timings
tEIH tEIL
EXI0 EXI1
0.8VDD 0.2VDD
- 24 -
CXP81952M/81960M
Appendix Fig. 10. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
10.00 HC-49/U03 12.00 16.00 8.00 HC-49/U (-S) 10.00 12.00 16.00 P3 32.768kHz 20.00 16 (12) 16 (12) 12 12 30 21 16 (12) 16 (12) 12 12 18 21 5 5
0
(i)
KINSEKI LTD.
0
(i)
470K 01
(ii) (i)
NIHON DENPA AT-51 KOGYO CO., LTD 1 Typical
Mask option table Item Reset pin pull-up resistor Non-existent Content Existent
- 25 -
CXP81952M/81960M
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical) 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 1/2 dividing mode 30 40
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
20.0 10.0
IDD - Supply current [mA]
5.0
1.0 0.5 32kHz mode (instruction)
IDD - Supply current [mA]
SLEEP mode
20 1/4 dividing mode
0.1 (100A) 0.05 (50A)
32kHz SLEEP mode
10 1/16 dividing mode
0.01 (10A) 3 4 5 6 0 5 10 16 fc - System clock [MHz]
SLEEP mode 20
VDD - Supply voltage [V]
IDD vs. VDD
(fc = 12MHz, Ta = 25C, Typical) 1/2 dividing mode 20.0 10.0 1/16 dividing mode 5.0 30 1/4 dividing mode 40
IDD vs. fc
(VDD = 3.0V, Ta = 25C, Typical)
IDD - Supply current [mA]
1.0 0.5
IDD - Supply current [mA]
SLEEP mode
20
0.1 (100A) 0.05 (50A)
1/2 dividing mode 10 1/4 dividing mode
0.01 (10A) 3 4 5 6 01 5 10 fc - System clock [MHz]
1/16 dividing mode SLEEP mode 15 VDD - Supply voltage [V]
- 26 -
CXP81952M/81960M
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
100PIN LQFP (PLASTIC)
16.0 0.2 75 76 14.0 0.1 51 50
100 1 0.5 0.08 + 0.08 0.18 - 0.03 25
26 (0.22)
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
LQFP-100P-L01 QFP100-P-1414-A
- 27 -
0.5 0.2
A
(15.0)

▲Up To Search▲

Price & Availability of CXP81952M

	To Download CXP81952M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .